In the field of high speed serial communications/data transfers between integrated circuits or systems, data recovery circuits are extensively used in transceivers. The performance of a data recovery circuit is intimately tied to its capacity to correctly recover the transmitted data when the clock period varies with time. It must also be able to deal with any type of troubles introduced by transmission channel artifacts as well as by modulation and pulse shaping components in the transmission paths. Therefore, to sustain high data rate, the data recovery circuit must be able to deal with these data perturbations usually referred to respectively as the jitter and intersymbol interference (ISI).
Consider a conventional data recovery circuit using the oversampling technique. Schematically, it first comprises an oversampling circuit that generates a plurality of data samples during each data period, an edge detection circuit, a selection determination circuit, a selection validation circuit and a selection memory that are connected in series. The role of these circuits is to determine which one of the data samples is the best to keep. It further comprises a data sample selection circuit. The memorized validated selection signals obtained at the output of the selection memory and the data samples are applied to this data sample selection circuit to generate the recovered data. The effect of the jitter is to decrease the width of the time interval in which the data signal can be reliably sampled. The effect of the ISI is to add a delay on the data stream depending on the past values of the data.
FIG. 1 is an example of a typical eye diagram for a high speed serial data link. Data jitter (and phase error between the reference clock and data as well) can significantly reduce the sampling window (hatched area) which thus becomes shorter than the bit period T. As apparent in FIG. 1, the edge positions (broken lines) can significantly move due to jitter (and ISI), in fact much more than illustrated, up to about 30% of the bit period in some cases. For data recovery circuits using the oversampling technique, the sampling window is determined from the edges or transitions of the data bit, so that accurately detecting edge positions is essential. It is also important to determine whether a particular detected data edge is representative or if it should be removed from the statistical processing of the data edges because it sits away from the group. A Data Edge Memory is then needed to memorize over an extended period of time the data edges so that they can be considered as a statistical result representative of the data eye diagram.
Consider the following examples of set of data edges from the Data Edge Memory: 00000000, 00010000, 00111000 and 01110100. There is no edge detected in the first example and one edge in the second example. In reality, due to the above mentioned perturbations, such a perfect detection never occurs. Example 3 is more realistic and the edge is detected at three consecutive positions. The problem raised by the maverick data edge is illustrated by example 4. Presence of a ‘0’ between two ‘1’s reveals an anomaly, typical of a maverick data edge related problem that should be understood and addressed. In addition to jitter and ISI, some sporadic perturbations can occur to add a delay on the data stream.
Among these sporadic perturbations, the detection of a data edge at an abnormal position with respect to other data edges is one of the most important, because it can lead to sample the data at non-optimum positions. This particular type of perturbations is referred to as a maverick data edge in the technical literature. Some attempts have been made in the prior art to statistically determine the normal edge positions and to dismiss any maverick data edge, the position of which would be spaced thereof. To detect such a notable shift from normality has been done using a battery of counters (one per sampling phase). As result, this solution is complex and expensive because it consumes a lot of silicon area when the data recovery circuit is integrated in silicon. For high speed data transfers, these sporadic delay perturbations can substantially decrease the capacity of the data recovery circuit to tolerate the normal cycle-to-cycle random data jitter. Therefore, it would be highly desirable to detect and then dismiss these maverick data edges.